Method and system for detecting potential reliability failures of integrated circuit

ABSTRACT

A method and system for detecting a potential reliability problem cause by electrical bridging in an integrated circuit. A voltage difference is created between two conducting lines in the integrated circuit to accelerate the bridging effect for a predetermined period of time. The conducting lines are detected to determine whether an undesired connection has occurred due to the bridging effect between the conducting lines.

This application is a division of application Ser. No. 10/841,083 filedMay 7, 2004, the entirety of which is incorporated by reference herein.

BACKGROUND

The present invention generally relates to testing integrated circuits,and more particularly to a method and system capable of detectingpotential reliability failures of memory chips.

“Bridging effect” is a term describing the formation of an undesiredelectrical connection between adjacent conducting lines in an integratedcircuit. One cause of the bridging effect is metal migration induced bya voltage difference between the adjacent lines. Such undesiredconnection often causes short circuits and system failures to theintegrated circuit. As wire space of integrated circuits becomesnarrower, the metal migration becomes easier and the bridging effectbecomes more troublesome. For embodiment, a memory chip has a pluralityof closely located word lines and bit lines defining addresses of memorycells. Conventionally, those word lines are composed of poly-siliconlines strapped with metal lines in order to reduce the RC effect. Thestrapped metal lines are particularly susceptible to the bridging effectbecause the metal migration may easily cross their narrow spacing. Thismay results in an undesired connection formed between the metal lines.Such undesired connection would cause unexpected voltage drop of signalson the word lines. As a result, the memory chip would not functionproperty.

It is difficult to detect such bridging effect in the manufacturingstage. An integrated circuit would undergo a number of tests forpurposes of quality control before it is released in the market.Conventionally, these tests input signals into the integrated circuitand check whether the output signals are correct. The signals areusually at an ordinary voltage level and lasts in the integrated circuitfor a short period of time. However, the metal migration is a long andgradual process that usually takes a long time for the migrate metal tofully develop as an electrical connection. An integrated circuit thatpasses the tests may still fail later on because of the undesiredconnection developed over a long period of operation. This wouldincrease the product return rate by the customers and raises a seriousreliability issue.

What is needed is a method and system capable of detecting potentialdefects caused by the bridging effect between adjacent lines in order toimprove the reliability of an integrated circuit.

SUMMARY

The invention comprises a method and system for detecting a potentialreliability issue. A voltage difference is created between twoconducting lines in the integrated for a predetermined period of timefor inducing the bridging effect therebetween. The two conducting linesare detected to determine whether an undesired connection has occurredtherebetween.

Various aspects and advantages will become apparent from the followingdetailed description, taken in conjunction with the accompanyingdrawings, illustrating the principles of the invention by way ofembodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a schematic of a conventional memory cell array.

FIG. 2 illustrates a localized area of the memory cell undergoing astress test according to an embodiment of the present invention.

FIG. 3 illustrates another localized area of the memory cell undergoingthe stress test according to an embodiment of the present invention.

FIG. 4 is a flowchart illustrating a process for erasing a memory chipwith the stress test according to an embodiment of the presentinvention.

FIG. 5 illustrates an exemplary circuit for selecting alternating worldlines for an erasure process according to an embodiment of the presentinvention.

DESCRIPTION

The invention presents a method and system for detecting potentialreliability failures due to the bridging effect between two conductinglines in an integrated circuit. The two lines are electrically stressedto create a voltage difference for a predetermined period of time inorder to accelerate the metal migration therebetween. An undesiredconnection between the stressed lines may occur as a result of the metalmigration. A testing signal is inputted to one or both of the stressedlines. Whether the undesired connection occurs can be determined bydetecting the output signal from the stressed lines. If the outputsignal fails to meet an expected standard, the undesired connectionoccurs. This means that the integrated circuit fails the reliabilitytest.

The invention is applicable to any integrated circuit including, but notlimited to, Programmable Read Only Memory (PROM), Erasable ProgrammableRead Only Memory (EPROM), Electrical Erasable Programmable Read OnlyMemory (EEPROM), Static Random Access Memory (SRAM), Dynamic RandomAccess Memory (DRAM), microprocessor, and other logic circuits. Theinvention will be described based on a non-volatile memory chip as oneembodiment in the following paragraphs.

FIG. 1 illustrates a memory cell array 30 having a plurality of memorycells arranged in rows and columns. A word line W₁, W₂, W₃ or W₄ runsthrough each row, and is connected to the control gates of the memorycells on that row. A bit line B₁, B₂, B₃ or B₄ runs through each column,and is connected to the drains of the memory cells on that column. Asource line S₁ or S₂ is connected to the source of two adjacent memorycells. This arrangement enables the data stored in the memory array 30to be read in a logical sense. For embodiment, when a reference voltage,V_(ref), is applied to word line W₁, the control gates along word lineW₁ will be turned on. The bit lines B₁, B₂, B₃ and B₄ will output binarydata stored in the memory cells along word line W₁.

The word lines are usually made of conductive material, such as metaland silicon based materials (including poly silicon). Because the wordlines are long and narrow, they suffer serious RC effects. The wordlines are often strapped with a metal layer in order to reduce theresistance and alleviate the RC effect. Given that the scale of a memorychip is in the degree of sub-μ meters or even lower, any two adjacentword lines would be very close to one another. The metal migration isrelatively easy between the adjacent word lines. In other words, theword lines are particularly susceptible to the bridging effect. Becausethe bridging effect may not occur until the memory chip has beenoperated over a significant period of time, it is not easily detected inthe manufacturing stage. In fact, such reliability problem is oftenfound by an end user after he has run the memory chip for a long time.This may result in a high product return rate. As such, it is desirableto accelerate the metal migration in order to detect the bridging effectin the manufacturing stage.

The rate of metal migration between two adjacent word lines depends onthe voltage difference therebetween. In order to create the voltagedifference, one world line would be raised to a high voltage level, andthe other adjacent word line would be maintained at a low voltage level.The greater the voltages difference, the higher the rate of metalmigration. Because the happening of the bridging effect depends not onlyon the rate of metal migration, but also the time for which the metalmigrates. A time would be predetermined for the adjacent word lines toundergo such voltage difference. The length of the predetermined timecan be based upon the magnitude of the voltage difference and therequirement of reliability. If an undesired connection occurs betweenthe word lines, they fail to meet the requirement of reliability.

FIG. 2 illustrates how to screen out an unreliable memory chip due tothe bridging effect, according to an embodiment of the presentinvention. A memory chip include a plurality of word lines as shown inthe figure. A high voltage (V_(H)) is applied to a word line 42 and anadjacent word line 44 is connected to a lower voltage level (V₀), suchas ground. The voltage difference between the word lines 42 and 44accelerates the metal migration therebetween. The voltage differencewill be held for a predetermined period of time for the metal migrationto form an undesired connection 46 therebetween. A signal is input intoone or both of the word lines 42 and 44. Reading an output signal fromthe word lines 42 and 44, if the output signal's voltage drops, it meansthe undesired connection has occurred. This indicates that the memorychip fails the reliability requirement.

This embodiment applies not only to two individually selected wordlines, but also to a group of word lines in a massive scale. A highvoltage may be applied to alternating word lines. A low voltage may beapplied to intervening word lines between the alternating word lines.Thus, those word lines can be tested together at one time.

There are alternative ways to detect a group of word lines according tothe embodiment. Referring to FIG. 3, a high voltage (V_(H)) is appliedto the first and fourth word lines for every four word lines. The secondand third word lines of every four word lines are connected to a lowvoltage level, such as ground. While this alternative groups the wordlines in a different way, the undesired connections caused by thebridging effect can be detected in the same manner as the aboveembodiment.

Note that the disclosed method can test any conductor other than wordlines. The conductor may be metal or semiconductor based materials, suchas poly-silicon. The migration of impurities in semiconductor materialsworks in a way similar to the metal migration. A voltage differencebetween two adjacent lines made of semiconductor materials acceleratesthe migration of impurities. This may also create an undesiredconnection caused by the bridging effect.

FIG. 4 shows a flowchart 50 of using the disclosed method to test amemory chip in a memory erase process, according to one embodiment ofthe invention. At step 52, the memory chip is stressed to create avoltage difference between adjacent word lines to accelerate the metalmigration. The way of creating such voltage difference is the same asthe discussion above. At step 54, a background voltage of the word linesis set to a low voltage level. At step 56, a first high voltage isapplied to alternating world lines to erase a first set of dataassociated thereto. Then a second high voltage is applied to interveningword lines that separate the alternating word lines to erase a secondset of data associated thereto. For embodiment, a high voltage isapplied to all of the odd word lines for a period of time, and thenapplied to all of the even word lines. The first high voltage may be thesame as or differ from the first high voltage. Note that at least one ortwo intervening word lines can be arranged between two alternating wordlines, as described in FIGS. 2 and 3. If there are any unreliable wordlines, an undesired connection will occur during the stressing. Theundesired connection will cause the high voltage drops inappropriatelyand results in the first and second sets of data erased incompletely andunsuccessfully. At step 58, the alternating and intervening conductinglines are detected to determine whether the first and second sets ofdata are fully erased, as an indication of the bridging effect'shappening. For embodiment, the signals outputted from the conductinglined can be read to determine whether the data associated to thoselines are erased. If the reading is not correct, it means that theerasure is not successful. This indicated that the undesired connectiondoes occur and the memory chip fails the test.

As it is understood that the memory chip has its own inputs and outputswhich allow the reading operation to happen. The voltage difference canbe created by connecting the word lines to a power supply. Further, adetection or compensation circuit is traditionally included to erase thevalue of the data stored in the memory chip. These hardware modules canbe used for the above described erasure and detection operations.

Conventionally, the reliability of a memory chip cannot be tested in anmemory erasing process. One reason is that in the memory erasing processall of the word line are raised to a high voltage. As a result, there isno voltage difference between the adjacent word lines, so that theconventional memory erasing process does not accelerate the metalmigration. As such, the disclosed memory erasing process has anadvantage of detesting the bridging effect in the memory erasingprocess.

FIG. 5 illustrates an exemplary selection circuit for selectingalternating lines for memory erasure. The circuit is composed of aninverter and three NAND gates. The truth table is presented as thefollowing: Address Time Erase Even Line Odd Line 0 0 0 1 0 1 0 0 0 1 0 01 1 1 1 0 1 1 1 0 1 0 1 0 1 1 0 0 1 0 1 1 1 0 1 1 1 0 1

For embodiment, when the inputs at nodes, Address, Time and Erase are 0,1 and 1, the output at the even line is 1 and the odd line is 0, whereinAddress designates an address of an memory cell, Erase designates anactivation of a erasure, and Time designates the time for the erasure.When the inputs at nodes, Address, Time and Erase are 1, 1 and 1, theoutput at the even line is 0 and at the odd line is 1.

Note that many other alternatives, either by hardware or software, canachieve the same result as the above selection circuit. The selectioncircuit may be an on-chip charge pump circuit, because this charge pumpprovides limited current and its level will be pull down if there isshort to ground.

This invention makes it possible to screen out integrated circuitshaving potential reliability problems caused by the bridging before theyare released to the end users. It can be used to detect the potentialreliability failure between any conductive lines in any integratedcircuit, such as Random Access Memory (RAM), PROM, EPROM, EEPROM, FlashMemory and Micro-Processor. The invention has a specific application tonon-volatile memory, because it can be used together with a memoryerasing process.

The above invention provides many different embodiments, or embodiments,for implementing different features of the invention. Specificembodiments of components, and processes are described to help clarifythe invention. These are, of course, merely embodiments and are notintended to limit the invention from that described in the claims.

Although illustrative embodiments of the invention have been shown anddescribed, other modifications, changes, and substitutions are intendedin the foregoing invention. Accordingly, it is appropriate that theappended claims be construed broadly and in a manner consistent with thescope of the invention, as set forth in the following claims.

1. A method for detecting a potential bridging effect between a firstconducting line and a second conducting line in an integrated circuit,the method comprising: creating a voltage difference between the firstconducting line and the second conducting line for a predeterminedperiod of time for inducing the bridging effect therebetween; anddetecting whether an undesired connection has occurred due to thebridging effect between the first conducting line and the secondconducting line.
 2. The method of claim 1 wherein the first conductingline is adjacent to the second conducting line.
 3. The method of claim 1wherein the first conducting line and the second conducting line aremade of metal or silicon-based materials.
 4. The method of claim 1wherein the creating a voltage difference further comprises: applying afirst voltage to the first conducting line; and applying a secondvoltage to the second conducting line wherein the first voltage ishigher than the second voltage.
 5. The method of claim 1 wherein: thefirst conducting line is adjacent to the second conducting line; thefirst conducting line and the second conducting line are made of metalor silicon-based materials; and the step of creating a voltagedifference further comprises: applying a first voltage to the firstconducting line; and applying a second voltage to the second conductingline wherein the first voltage is higher than the second voltage.
 6. Asystem for detecting a potential bridging effect between a firstconducting line and a second conducting line in an integrated circuit,the system comprising: means for creating a voltage difference betweenthe first conducting line and the second conducting line for apredetermined period of time for inducing the bridging effecttherebetween; and means for detecting whether a connection has occurreddue to the bridging effect between the first conducting line and thesecond conducting line.
 7. The system of claim 6 wherein the firstconducting line is adjacent to the second conducting line.
 8. The systemof claim 7 wherein the integrated circuit is a memory chip.
 9. Thesystem of claim 8 wherein the means for creating a voltage differencefurther comprises a selection circuit for selectively raising the firstconducting line or the second conducting line to a high voltage level.10. The system of claim 9 wherein the selection circuit selects thefirst conducting line or the second conducting line in response toinputs designating an address of a memory cell and an activation of adata erasure.
 11. The system of claim 10 wherein the selection circuitis further responsive to an input designating the predetermined periodof time.
 12. The system of claim 6 wherein the integrated circuit is amemory chip.
 13. The system of claim 6 wherein the means for creating avoltage difference further comprises a selection circuit for selectivelyraising the first conducting line or the second conducting line to ahigh voltage level.
 14. The system of claim 13 wherein the selectioncircuit selects the first conducting line or the second conducting linein response to inputs designating an address of a memory cell and anactivation of a data erasure.
 15. The system of claim 13 wherein theselection circuit is further responsive to an input designating thepredetermined period of time.